/*****************************************************************************
*    Copyright (C)2003 Ali Corporation. All Rights Reserved.
*
*    File:    nim_s3503_DVBS.h
*
*    Description:    Header file in LLD.
*    History:
*   		Date			Athor   	 	Version		  				Reason
*	============	=======	===============	=================
*   	1.  08/29/2012  	Russell		 	Ver 0.1			 Create file for S3503 DVBS2 project
*
*****************************************************************************/

#ifndef __LLD_NIM_S3503_H__
#define __LLD_NIM_S3503_H__

#include "Porting.h"
//#include "nim_dev.h"
//#define NIM_3501_FUNC_EXT

#define	FFT_BITWIDTH			10
#define	STATISTIC_LENGTH		2

//average length of data to determine threshold
//0:2;1:4;2:8

#define NIM_S3503_BASE_ADDR  0xB8028000
#define NIM_S3503_SUB_ID  0x0
#define NIM_C3503_SUB_ID  0x1

#define	MAX_CH_NUMBER			32//maximum number of channels that can be stored
#define s3501_LOACL_FREQ   		5150
#define s3501_DEBUG_FLAG		0
#define QPSK_TUNER_FREQ_OFFSET	4
#define M3501_IQ_AD_SWAP   		0x04
#define M3501_EXT_ADC   	   	0x02
#define M3501_QPSK_FREQ_OFFSET 	0x01
#define M3501_I2C_THROUGH   	0x08
#define M3501_NEW_AGC1  		0x20
#define M3501_POLAR_REVERT  	0x10
#define M3501_1BIT_MODE 		0x00 
#define M3501_2BIT_MODE 		0x40
#define M3501_4BIT_MODE 		0x80
#define M3501_8BIT_MODE 		0xc0
#define M3501_AGC_INVERT		0x100
//#define M3501_SPI_SSI_MODE	0x200     8bit mode(SPI) 1bit mode(SSI)
#define M3501_USE_188_MODE		0x400
#define M3501_DVBS_MODE			0x00	
#define M3501_DVBS2_MODE		0x01
#define M3501_SIGNAL_DISPLAY_LIN	0x800




#define NIM_GET_DWORD(i)	(*(volatile UINT32 *)(i))
#define NIM_SET_DWORD(i,d)  (*(volatile UINT32 *)(i)) = (d)

#define NIM_GET_WORD(i) 	(*(volatile UINT16 *)(i))
#define NIM_SET_WORD(i,d)   (*(volatile UINT16 *)(i)) = (d)

#define NIM_GET_BYTE(i) 	(*(volatile UINT8 *)(i))
#define NIM_SET_BYTE(i,d)   (*(volatile UINT8 *)(i)) = (d)

#define S3501_FREQ_OFFSET 1
#define LNB_LOACL_FREQ 5150
#define AS_FREQ_MIN 900
#define AS_FREQ_MAX 2200

#define NIM_OPTR_CHL_CHANGE0		0x70
#define NIM_OPTR_CHL_CHANGE			0x00
#define NIM_OPTR_SOFT_SEARCH		0x01
#define NIM_OPTR_FFT_RESULT			0x02
#define NIM_OPTR_DYNAMIC_POW		0x03
#define NIM_OPTR_DYNAMIC_POW0		0x73
#define NIM_OPTR_IOCTL				0x04
#define NIM_OPTR_HW_OPEN			0x05
#define NIM_OPTR_HW_CLOSE			0x06

#define NIM_DEMOD_CTRL_0X50			0x50
#define NIM_DEMOD_CTRL_0X51			0x51
#define NIM_DEMOD_CTRL_0X90			0x90
#define NIM_DEMOD_CTRL_0X91			0x91
#define NIM_DEMOD_CTRL_0X02			0x02
#define NIM_DEMOD_CTRL_0X52			0x52

#define NIM_SIGNAL_INPUT_OPEN		0x01
#define NIM_SIGNAL_INPUT_CLOSE		0x02

#define NIM_LOCK_STUS_NORMAL		0x00
#define NIM_LOCK_STUS_SETTING		0x01
#define NIM_LOCK_STUS_CLEAR			0x02

#define NIM_FLAG_CHN_CHG_START		(1<<0)
#define NIM_FLAG_CHN_CHANGING		(1<<1)
#define NIM_SWITCH_TR_CR			0x01
#define NIM_SWITCH_RS				0x02
#define NIM_SWITCH_FC				0x04
#define NIM_SWITCH_HBCD				0x08

#define TS_DYM_HEAD0 				0x47
#define TS_DYM_HEAD1 				0x1f
#define TS_DYM_HEAD2 				0xff
#define TS_DYM_HEAD3 				0x10
#define TS_DYM_HEAD4 				0x00
 //------------------------ defines for CR adaptive ---------------------------------
#define SNR_TAB_SIZE 19 // for SI, use macro instead of enum
#define PSK8_TAB_SIZE 14
#define QPSK_TAB_SIZE 3
#define APSK16_TAB_SIZE 11
static UINT8 SNR_dBX10_TAB[SNR_TAB_SIZE] = {30, 40, 50,
	  60, 65, 70, 75, 80, 85, 90, 95, 100, 105,110,115,120,140,160,180};
// 1st column : >=thr, switch to lower snr, also use for initial search
// 2nd column: <=thr, switch to high snr
static const UINT16 SNR_THR[SNR_TAB_SIZE*2] = {
	                    956, 1060, // 3
					    837, 893, // 4
					    713, 775, // 5
					    690, 725, // 6,  8SPK start**
	      				630, 677, // 6.5	
	      				573, 615, // 7		
	      				520, 559, // 7.5  
	      				470, 508, // 8    
	      				426, 460, // 8.5  
	      				386, 415, // 9    // 16 APSK start
	      				347, 376, // 9.5  
	      				313, 339, // 10   
	      				281, 303, // 10.5 //
	      				253, 275,  // 11  
	      				228, 246,  // 11.5
	      				205, 222, // 12   **
	      				113, 144, // 14
	      				74, 91, // 16
	      				0, 60 // 18
					};

// head gain have 3 bit, in SW Tab, using 4bit for better understanding
//{IRS[4:0],  PRS[3:0], HEAD_GAIN[3:0],FRAC[3:0],}
// for 8PSK 3/5  add by grace
static const UINT32 CR_PARA_8PSK_3f5[PSK8_TAB_SIZE] = { 
       		0x12930,  //6
       		0x12930,  //6.5
       		0x12900,  //7
       		0x11800,  //7.5
       		0x1070a,  //8
       		0x10705,  //8.5
       		0x10705,  //9
       		0x10705,  //9.5
       		0x10705,  //10
			0x10705,  // 10.5
			0x10705,  // 11
			0x10705,  // 11.5
			0x10700,  // 12
			0x10700   // 14
		};

// for 8PSK other coderate 9/10,8/9,5/6,3/4,2/3  add by grace
static const UINT32 CR_PARA_8PSK_others[PSK8_TAB_SIZE] = { 
			0x12930, // 6
			0x12910, // 6.5
			0x12900, // 7
			0x11900, // 7.5
			0x11800, // 8
			0x11800, // 8.5
			0x1070a, // 9
			0x1070a, // 9.5
			0x10705, // 10
			0x10705,  // 10.5
			0x1070a, // 11
			0x10705, // 11.5
			0x10700, // 12
			0x10700  // 14
		};

// Begin: TAB for New ADPT Add by Hongyu //
/*
1) S2_CODE_RATE_TABLE size = 28*30 = 840 bits
index = {code_rate}, 28 index
value = { //30 bits
        S2_AWGN_NOISE,             //10 bits, EST_NOISE (MSBs) level to apply AWGN coefficients
        S2_AWGN_COEF_SET,  //3 bit, select one set from the AWGN_COEF table
        S2_PON_IRS_DELTA,  //3 bit signed, subtract from AWGN IRS when Pilot On
        S2_PON_PRS_DELTA,  //3 bit signed, subtract from AWGN PRS when Pilot On
        S2_LOOP_COEF_SET,  //3 bit, select one set from the CLIP_PED table
        S2_CLIP_PED_SET,   //3 bit, select one set from the CLIP_PED table
        S2_AVG_PED_SET,    //3 bit, select one set from the AVG_PED table
        S2_FORCE_OLD_CR,   //1 bit, only affect pilot off
        S2_LLR_SHIFT ,             //1 bit
        } 
code_rate = PL_MODCOD_TYPE[6:2]-1;

*/
static const UINT16 S2_AWGN_NOISE[28]={ // 10bits
// 
    0x1ff,//"QPSK 1/4", // 1 <=0.4dB
	0x1ff,//"QPSK 1/3", // 2
	0x1ff,//"QPSK 2/5", // 3
    0x005,//0x1ed,//"QPSK 1/2", // 4 1.7dB
	0x1bc,//0x1c3,//"QPSK 3/5", // 5 2.6dB
	0x1ff,//"QPSK 2/3", // 6 3.6dB
	0x1ff,//"QPSK 3/4", // 7 4.5dB
	0x1ff,//"QPSK 4/5", // 8 5.2dB
	0x1ff,//"QPSK 5/6", // 9 5.6dB
	0x1ff,//"QPSK 8/9", // 10
	0x1ff,//"QPSK 9/10", // 11 I set to 0x1ff because the value is small to 0x115 at the AWGN, but at the phase noise
			// when the CR is locked, the EST_NOISE is high to 0x15a, and so that the widerloop cannot be openecd.
			// and then CR will be unlocked.
			// this setting does not effect the AWGN performance.
    // symbol rate 6500below:   up
    0xcd,  //"8PSK 3/5", 6.5dB
	0xb9, //"8PSK 2/3", // 13 7.5dB
	0xa5,  //"8PSK 3/4", // 14 8.6dB
	0x90, //"8PSK 5/6", // 15 9.7dB
	0x83,//"8PSK 8/9", // 16 11.1dB phase noise
	0x83,//"8PSK 9/10", // 17 11.1dB(Phase noise)
	0x5f,//"16APSK 2/3", // 18 11.5dB
	0x59,//"16APSK 3/4", // 19 12.0dB
	0x56,//"16APSK 4/5", // 20 12.3dB0
	0x57,//"16APSK 5/6", // 21 12.2dB
	0x47,//"16APSK 8/9", // 22 13.6dB(phase noise)
	0x46,//"16APSK 9/10", // 23 13.7dB(phase noise)
	0x35,//"32APSK 3/4", // 24 14.3dB(phase noise)
	0x31,//"32APSK 4/5", // 25 15.3dB(phase noise)
	0x30,//"32APSK 5/6", // 26 15.5dB(phase noise)
	0x26,//"32APSK 8/9", // 27 16.70dB
	0x22//"32APSK 9/10", // 28 17.3dB
	};

static const UINT16 S2_AWGN_NOISE_EXTRA[28]={ // 10bits
// 6.5<=symbol_rate<=33M
    0x1ff,//"QPSK 1/4", // 1 <=0.4dB
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0,//x190,//"QPSK 1/2",3.0dB awgn for wider loop enable
	0x1ff,//"QPSK 3/5", // 5 same to QPSK 8/9
	0x1ff,//"QPSK 2/3", // 6
	0x1ff,//"QPSK 3/4", // 7
	0x1ff,//"QPSK 4/5", // 8
	0x1ff,//"QPSK 5/6", // 9
	0x1ff,//"QPSK 8/9", // 10
	0x1ff,//"QPSK 9/10", // 11 I set to 0x1ff because the value is small to 0x115 at the AWGN, but at the phase noise
			// when the CR is locked, the EST_NOISE is high to 0x15a, and so that the widerloop cannot be openecd.
			// and then CR will be unlocked.
			// this setting does not effect the AWGN performance.
    // symbol rate 6500below:   up
    0xc0, //"8PSK 3/5", // 12 6.5dB
	0xb0, //"8PSK 2/3", // 13 7.5dB
	0x9e, //"8PSK 3/4", // 14 8.6dB
	0x8c, //"8PSK 5/6", // 15 9.7dB
	0x7a,//"8PSK 8/9", // 16 11.1dB phase noise
	0x7a,//"8PSK 9/10", // 17 11.1dB(Phase noise)
	0x5b,//"16APSK 2/3", // 18 11.5dB
	0x55,//"16APSK 3/4", // 19 12.0dB
	0x54,//"16APSK 4/5", // 20 12.3dB0
	0x54,//"16APSK 5/6", // 21 12.2dB
	0x47,//"16APSK 8/9", // 22 13.6dB(phase noise)
	0x43,//"16APSK 9/10", // 23 14.0 awgn    //(dont use)->13.7dB(phase noise)
	0x33,//"32APSK 3/4", // 24 14.3dB(phase noise)
	0x2e,//"32APSK 4/5", // 25 15.3dB(phase noise)
	0x2d,//"32APSK 5/6", // 26 15.5dB(phase noise)
	0x25,//"32APSK 8/9", // 27 16.70dB
	0x23//"32APSK 9/10", // 28 17.3dB
	};

static const UINT8 S2_AWGN_COEF_SET[28]={//3	//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x2,//0x1,//"QPSK 1/2", // 4
	0x6,//"QPSK 3/5", // 5
	0x7,//"QPSK 2/3", // 6
	0x0,//"QPSK 3/4", // 7
	0x2,//"QPSK 4/5", // 8  0x0////
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0x1,//"QPSK 9/10", // 11
	0x0,//"8PSK 3/5", // 12
	0x3,//"8PSK 2/3", // 13
	0x3,//"8PSK 3/4", // 14
	0x3,//"8PSK 5/6", // 15
	0x2,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x2,//"16APSK 2/3", // 18
	0x0,//"16APSK 3/4", // 19
	0x1,//"16APSK 4/5", // 20
	0x2,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0x0,//"16APSK 9/10", // 23
	0,//"32APSK 3/4", // 24
	0x0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x2,//"32APSK 8/9", // 27
	0x2//"32APSK 9/10", // 28
	};
static const UINT8 S2_AWGN_COEF_SET_EXTRA[28]={//3	//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x2,//0x1,20130703//"QPSK 1/2", // 4
	0x1,//"QPSK 3/5", // 5
	0x6,//"QPSK 2/3", // 6
	0x6,//"QPSK 3/4", // 7
	0x1,//"QPSK 4/5", // 8
	0x6,//"QPSK 5/6", // 9
	0x6,//"QPSK 8/9", // 10
	0x6,//"QPSK 9/10", // 11
	0x1,//"8PSK 3/5", // 12
	0x3,//"8PSK 2/3", // 13
	0x3,//"8PSK 3/4", // 14
	0x3,//"8PSK 5/6", // 15
	0x2,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x4,//"16APSK 2/3", // 18
	0x0,//"16APSK 3/4", // 19
	0x2,//"16APSK 4/5", // 20
	0x2,//"16APSK 5/6", // 21
	0x1,//"16APSK 8/9", // 22
	0x1,//"16APSK 9/10", // 23
	0,//"32APSK 3/4", // 24
	0x0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0x5//"32APSK 9/10", // 28
	};

static const UINT8 S2_PON_IRS_DELTA[28]={//4	//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x0,//"QPSK 1/2", // 4
	0x7,//"QPSK 3/5", // 5
	0x1,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	0x7,//"8PSK 3/5", // 12
	0x0,//"8PSK 2/3", // 13
	0x0,//"8PSK 3/4", // 14
	0x0,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x0,//"16APSK 2/3", // 18
	0x0,//"16APSK 3/4", // 19
	0x0,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0x7,//"32APSK 3/4", // 24
	0x7,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0x1//"32APSK 9/10", // 28
	};
static const UINT8 S2_PON_IRS_DELTA_EXTRA[28]={//4	//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x6,//0x0,//"QPSK 1/2", // 4
	0x1,//"QPSK 3/5", // 5
	0,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	0x7,//"8PSK 3/5", // 12
	0x0,//"8PSK 2/3", // 13
	0x0,//"8PSK 3/4", // 14
	0x7,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x7,//"16APSK 2/3", // 18
	0x7,//"16APSK 3/4", // 19
	0x7,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0x7,//"32APSK 3/4", // 24
	0x7,//"32APSK 4/5", // 25
	0x7,//"32APSK 5/6", // 26
	0x7,//"32APSK 8/9", // 27
	0x7//"32APSK 9/10", // 28
	};

static const UINT8 S2_PON_PRS_DELTA[28]={ // 3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x0,//"QPSK 1/2", // 4
	0x7,//"QPSK 3/5", // 5
	0x7,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	0x7,//"8PSK 3/5", // 12
	0x0,//"8PSK 2/3", // 13
	0x0,//"8PSK 3/4", // 14
	0x0,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x0,//"16APSK 2/3", // 18
	0x0,//"16APSK 3/4", // 19
	0x0,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0x7,//"32APSK 3/4", // 24
	0x7,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0x1//"32APSK 9/10", // 28
	};
static const UINT8 S2_PON_PRS_DELTA_EXTRA[28]={ // 3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x6,//0x0,//"QPSK 1/2", // 4
	0x7,//"QPSK 3/5", // 5
	0,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	0x7,//"8PSK 3/5", // 12
	0x0,//"8PSK 2/3", // 13
	0x0,//"8PSK 3/4", // 14
	0x7,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x0,//"8PSK 9/10", // 17
	0x7,//"16APSK 2/3", // 18
	0x7,//"16APSK 3/4", // 19
	0x7,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0x1,//"16APSK 8/9", // 22
	0x7,//"16APSK 9/10", // 23
	0x7,//"32APSK 3/4", // 24
	0x7,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0x1//"32APSK 9/10", // 28
	};

static const UINT8 S2_LOOP_COEF_SET[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x1,//"QPSK 1/2", // 4
	0x7,//"QPSK 3/5", // 5
	0x4,//"QPSK 2/3", // 6
	0x4,//"QPSK 3/4", // 7
	0x4,//"QPSK 4/5", // 8
	0x4,//"QPSK 5/6", // 9
	0x4,//"QPSK 8/9", // 10
	0x1,//"QPSK 9/10", // 11
	0x6,//"8PSK 3/5", // 12
	0x6,//"8PSK 2/3", // 13
	0x5,//"8PSK 3/4", // 14
	0x5,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x5,//"8PSK 9/10", // 17
	0,//"16APSK 2/3", // 18
	0,//"16APSK 3/4", // 19
	0x3,//"16APSK 4/5", // 20
	0x2,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0x4,//"16APSK 9/10", // 23
	0x0,//"32APSK 3/4", // 24
	0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0,//"32APSK 8/9", // 27
	0//"32APSK 9/10", // 28
};
static const UINT8 S2_LOOP_COEF_SET_EXTRA[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x1,//"QPSK 1/2", // 4
	0x7,//"QPSK 3/5", // 5
	0x1,//"QPSK 2/3", // 6
	0x1,//"QPSK 3/4", // 7
	0x7,//"QPSK 4/5", // 8
	0x1,//"QPSK 5/6", // 9
	0x1,//"QPSK 8/9", // 10
	0x1,//"QPSK 9/10", // 11
	0x7,//"8PSK 3/5", // 12
	0x5,//"8PSK 2/3", // 13
	0x2,//"8PSK 3/4", // 14
	0x5,//"8PSK 5/6", // 15
	0x7,//"8PSK 8/9", // 16
	0x5,//"8PSK 9/10", // 17
	0x3,//"16APSK 2/3", // 18
	0,//"16APSK 3/4", // 19
	0,//"16APSK 4/5", // 20
	0x2,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0x1,//"16APSK 9/10", // 23
	0x0,//"32APSK 3/4", // 24
	0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0,//"32APSK 8/9", // 27
	0x3//"32APSK 9/10", // 28
};

static const UINT8 S2_CLIP_PED_SET[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x4,//"QPSK 1/2", // 4
	0x2,//"QPSK 3/5", // 5
	0x4,//"QPSK 2/3", // 6
	0x4,//"QPSK 3/4", // 7
	0x4,//"QPSK 4/5", // 8
	0x4,//"QPSK 5/6", // 9
	0x4,//"QPSK 8/9", // 10
	0x2,//"QPSK 9/10", // 11
	0x0,//"8PSK 3/5", // 12
	0,//"8PSK 2/3", // 13
	0,//"8PSK 3/4", // 14
	0x0,//"8PSK 5/6", // 15
	1,//"8PSK 8/9", // 16
	0x2,//"8PSK 9/10", // 17
	0,//"16APSK 2/3", // 18
	0,//"16APSK 3/4", // 19
	0x2,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0x2,//"32APSK 3/4", // 24
	0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0//"32APSK 9/10", // 28
};
static const UINT8 S2_CLIP_PED_SET_EXTRA[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x2,//"QPSK 1/2", // 4
	0x4,//"QPSK 3/5", // 5
	0x2,//"QPSK 2/3", // 6
	0x2,//"QPSK 3/4", // 7
	0x4,//"QPSK 4/5", // 8
	0x2,//"QPSK 5/6", // 9
	0x2,//"QPSK 8/9", // 10
	0x2,//"QPSK 9/10", // 11
	0,//"8PSK 3/5", // 12
	0,//"8PSK 2/3", // 13
	0,//"8PSK 3/4", // 14
	0,//"8PSK 5/6", // 15
	1,//"8PSK 8/9", // 16
	0x2,//"8PSK 9/10", // 17
	0x0,//"16APSK 2/3", // 18
	0x2,//"16APSK 3/4", // 19
	0x2,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0x2,//"32APSK 3/4", // 24
	0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0x0,//"32APSK 8/9", // 27
	0//"32APSK 9/10", // 28
};

static const UINT8 S2_AVG_PED_SET[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x7,//"QPSK 1/2", // 4
	0x5,//"QPSK 3/5", // 5
	0x5,//"QPSK 2/3", // 6
	0x5,//"QPSK 3/4", // 7
	0x5,//"QPSK 4/5", // 8
	0x5,//"QPSK 5/6", // 9
	0x5,//"QPSK 8/9", // 10
	0x7,//"QPSK 9/10", // 11
	0,//"8PSK 3/5", // 12
	0x1,//"8PSK 2/3", // 13
	0x1,//"8PSK 3/4", // 14
	0x2,//"8PSK 5/6", // 15
	0x3,//"8PSK 8/9", // 16
	0x3,//"8PSK 9/10", // 17
	0,//"16APSK 2/3", // 18
	0x2,//"16APSK 3/4", // 19
	0,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0x2,//"16APSK 8/9", // 22
	0x2,//"16APSK 9/10", // 23
	0x5,//"32APSK 3/4", // 24
	0x5,//"32APSK 4/5", // 25
	0x5,//"32APSK 5/6", // 26
	0x5,//"32APSK 8/9", // 27
	0x5//"32APSK 9/10", // 28
};

static const UINT8 S2_AVG_PED_SET_EXTRA[28]={ //3//3bit
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0x7,//"QPSK 1/2", // 4
	0x5,//"QPSK 3/5", // 5
	0x5,//"QPSK 2/3", // 6
	0x5,//"QPSK 3/4", // 7
	0x6,//"QPSK 4/5", // 8
	0x5,//"QPSK 5/6", // 9
	0x5,//"QPSK 8/9", // 10
	0x5,//"QPSK 9/10", // 11
	0,//"8PSK 3/5", // 12
	0x1,//"8PSK 2/3", // 13
	0x1,//"8PSK 3/4", // 14
	0x6,//"8PSK 5/6", // 15
	0x3,//"8PSK 8/9", // 16
	0x3,//"8PSK 9/10", // 17
	0,//"16APSK 2/3", // 18
	0x2,//"16APSK 3/4", // 19
	0,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0x2,//"16APSK 8/9", // 22
	0x2,//"16APSK 9/10", // 23
	0x5,//"32APSK 3/4", // 24
	0x5,//"32APSK 4/5", // 25
	0x5,//"32APSK 5/6", // 26
	0x5,//"32APSK 8/9", // 27
	0x5//"32APSK 9/10", // 28
};


static const UINT8 S2_FORCE_OLD_CR[28]={
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0,//"QPSK 1/2", // 4
	0,//"QPSK 3/5", // 5
	0x1,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	0,//"8PSK 3/5", // 12
	0,//"8PSK 2/3", // 13
	0,//"8PSK 3/4", // 14
	0,//"8PSK 5/6", // 15
	1,//"8PSK 8/9", // 16
	0,//"8PSK 9/10", // 17
	0,//"16APSK 2/3", // 18
	0,//"16APSK 3/4", // 19
	0,//"16APSK 4/5", // 20
	0,//"16APSK 5/6", // 21
	0,//"16APSK 8/9", // 22
	0,//"16APSK 9/10", // 23
	0,//"32APSK 3/4", // 24
	0,//"32APSK 4/5", // 25
	0,//"32APSK 5/6", // 26
	0,//"32APSK 8/9", // 27
	0//"32APSK 9/10", // 28
};
static const UINT8 S2_LLR_SHIFT[28]={
	0,//"QPSK 1/4", // 1
	0,//"QPSK 1/3", // 2
	0,//"QPSK 2/5", // 3
    0,//"QPSK 1/2", // 4
	0,//"QPSK 3/5", // 5
	0,//"QPSK 2/3", // 6
	0,//"QPSK 3/4", // 7
	0,//"QPSK 4/5", // 8
	0,//"QPSK 5/6", // 9
	0,//"QPSK 8/9", // 10
	0,//"QPSK 9/10", // 11
	1,//"8PSK 3/5", // 12
	1,//"8PSK 2/3", // 13
	1,//"8PSK 3/4", // 14
	1,//"8PSK 5/6", // 15
	1,//"8PSK 8/9", // 16
	1,//"8PSK 9/10", // 17
	1,//"16APSK 2/3", // 18
	1,//"16APSK 3/4", // 19
	1,//"16APSK 4/5", // 20
	1,//"16APSK 5/6", // 21
	1,//"16APSK 8/9", // 22
	1,//"16APSK 9/10", // 23
	1,//"32APSK 3/4", // 24
	1,//"32APSK 4/5", // 25
	1,//"32APSK 5/6", // 26
	1,//"32APSK 8/9", // 27
	1//"32APSK 9/10", // 28
}; 

// here CODE_RATE_TABLE and other 4 tables, i implement it through like below and dont define these table 
// but its subtables

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/*
2) AWGN_COEF_TABLE size = 8 * 17 = 136 bits  //AVG_PED and Wider_Loop and disabled for AWGN, SYMBOL_BEFORE_HEAD only affect pilot off
index = {AWGN_COEF_SET} 8 index
value = {
        IRS,                            //5 bits, IRS_TRA_S2 for AWGN
        IRS_FRACTION,           //2 bits
        PRS,                            //4 bits
        PRS_FRACTION,           //2 bits
        HEAD_PED_GAIN,          //3 bits
        SYMBOL_BEFORE_HEAD      //1 bit, only affect pilot off with AWGN SNR
        }
*/
static const UINT8 SYMBOL_BEFORE_HEAD[8]={
	//						-AWGN_COEF_SET			
		1,				// 8psk 3/5;
		1,				// 8psk 2/3; 
		1,				//
		1,				//
		0,				// for DVBS
		0,				// dont use
		1,				// dotn use
		0				//
	};
static const UINT8 HEAD_PED_GAIN[8]={
		//						-AWGN_COEF_SET			
		0x1,			//  8psk 3/5;
		0x1,			//	8psk 2/3;
		0x1,				//	010
		0x1,				//	011
		0,				//  for DVBS
		0,				//	101
		0,				//	110
		0x1				//	111
	};
static const UINT8 PRS_FRACTION[8]={
		//						-AWGN_COEF_SET			
		0x3,//0x0				//  8psk 3/5;
		0,				//	8psk 2/3;
		0,				//	010
		0x2,///0				//	011
		0,				//  for DVBS
		0,				//	101
		0,				//	110
		0				//	111	
};
static const UINT8 PRS[8]={
		//						-AWGN_COEF_SET			
		0x7,			//  8psk 3/5;
		0x9,			//	8psk 2/3;
		0x8,				//	010
		0x7,				//	011
		0x8,				//  for DVBS
		0x0,				//	101
		0x9,				//	110
		0x7				//	111
};
static const UINT8 IRS_FRACTION[8]={
		//						-AWGN_COEF_SET			
		0x3,	//0x0			//  8psk 3/5;
		0,				//	8psk 2/3;
		0,				//	010
		0x2,//0				//	011
		0,				//  for DVBS
		0,				//	101
		0,				//	110
		0				//	111
};
static const UINT8 IRS[8]={
		//						-AWGN_COEF_SET			
		0x13,			//  8psk 3/5;
		0x12,			//	8psk 2/3;
		0x11,				//	010
		0x10,				//	011
		0x11,				//  for DVBS
		0x0,				//	101
		0x12,				//	110
		0x13				//	111
};
//----------6.5M to 33M begin--------------------------
static const UINT8 SYMBOL_BEFORE_HEAD_EXTRA[8]={
	//						-AWGN_COEF_SET			
		1,				// 8psk 3/5;
		1,				// 8psk 2/3; 
		1,				//
		1,				//
		1,				// dont use
		1,				// dont use
		1,				// dotn use
		0				//
	};
static const UINT8 HEAD_PED_GAIN_EXTRA[8]={
		//						-AWGN_COEF_SET			
		0x1,			//  8psk 3/5;
		0x1,			//	8psk 2/3;
		0x1,				//	010
		0x1,				//	011
		0,				//  100
		0,				//	101
		0,				//	110
		0x0				//	111
	};
static const UINT8 PRS_FRACTION_EXTRA[8]={
		//						-AWGN_COEF_SET			
		0x3,//0x0				//  8psk 3/5;
		0,				//	8psk 2/3;
		0,				//	010
		0x2,///0				//	011
		0,				//  100
		0,				//	101
		0,				//	110
		0				//	111	
};
static const UINT8 PRS_EXTRA[8]={
		//						-AWGN_COEF_SET			
		0x7,			//  8psk 3/5;
		0x9,			//	8psk 2/3;
		0x8,				//	010
		0x7,				//	011
		0xa,				//  100
		0xb,				//	101
		0x9,				//	110
		0x7				//	111
};
static const UINT8 IRS_FRACTION_EXTRA[8]={
		//						-AWGN_COEF_SET			
		0x3,	//0x0			//  8psk 3/5;
		0,				//	8psk 2/3;
		0,				//	010
		0x2,//0				//	011
		0,				//  100
		0,				//	101
		0,				//	110
		0				//	111
};
static const UINT8 IRS_EXTRA[8]={
		//						-AWGN_COEF_SET			
		0x13,			//  8psk 3/5;
		0x12,			//	8psk 2/3;
		0x11,				//	010
		0x10,				//	011
		0x13,				//  100
		0x14,				//	101
		0X12,				//	110
		0x13				//	111
};


/*
3) LOOP_COEF_TABLE size = 8 * 19 = 152 bits
index = {LOOP_COEF_SET} 8 index
value = {
        HEAD_GAIN_SNR_DELTA,    //3 bits, SNR_DELTA (dB) to disable HEAD_PED_GAIN, if HEAD_PED_GAIN is big, disable it result in big bandwidth increase
        MAX_SNR_DELTA,                  //3 bits, clip SNR_DELTA so that the bandwidth doesn't become too big for high SNR_DELTA
        IRS_STEP,                               //3 bits, IRS step for each SNR_DELTA, have 2 bits fraction (same as IRS_FRACTION)
        PRS_STEP,                               //3 bits
        WIDER_SNR_DELTA,                //3 bits, SNR_DELTA to enable WIDER_LOOP, =7 means WIDER_LOOP always disabled
        WIDER_IRS_DELTA,                //2 bits
        WIDER_PRS_DELTA                 //2 bits
        }
*/
static const UINT8 WIDER_PRS_DELTA[8]={
//						-LOOP_COEF_SET			
		0x2,				// dont touch
		0x2,				//dont touch
		0,				//	dont touch
		0x2,				//	011
		2,				//  dont touch
		0,				//	101
		0,				//	110
		0				//	dont touch
	};
static const UINT8 WIDER_IRS_DELTA[8]={
//						-LOOP_COEF_SET			
		0x2,				//  dont touch
		0x2,				//	dont touch
		0,				//	dont touch
		0x2,				//	011
		2,				//  dont touch
		0,				//	101
		0,				//	110
		0				//	dont touch
	};
static const UINT8 WIDER_SNR_DELTA[8]={
//						-LOOP_COEF_SET			
		0x7,				//  dont touch
		0x0,				//dont touch
		0x7,				//	dont touch
		0x5,				//	011
		0x7,				//  dont touch
		0x7,				//	101
		0x7,				//	110
		0x7				//	dont touch
	};
static const UINT8 PRS_STEP[8]={
//						-LOOP_COEF_SET			
		0x3,			//  dont touch
		0x0,			//	dont touch
		0x4,			//	dont touch
		0x4,			//	011 1*7
		0x0,				//  dont touch
		0x6,				//	101 6*1
		0x2,				//	110 2*3
		0x7				//	dont touch
	};
static const UINT8 IRS_STEP[8]={
//						-LOOP_COEF_SET			
		0x3 ,			//  dont touch
		0,			//	dont touch
		0x4,				//	dont touch
		0x4,				//	011
		0x0,				//  dont touch
		0x6,				//	101
		0x2,				//	110
		0x7				//	dont touch
	};
static const UINT8 MAX_SNR_DELTA[8]={
//						-LOOP_COEF_SET			
		0x1,			//  dont touch
		0x1,			//	dont touch
		0x1,				//	dont touch
		0x2,				//	011 1*7
		0x1,				//  dont touch
		0x1,				//	101 6*1
		0x3,				//	110 2*3
		0x1				//	dont touch
	};
static const UINT8 HEAD_GAIN_SNR_DELTA[8]={
//						-LOOP_COEF_SET			
		0x4,			// dont touch
		0x0,			//	dont touch
		0x2,				//	dont touch
		0x2,				//	011
		0x2,				//  dont touch
		0x2,				//	101
		0x2,				//	110
		0x2				//	dont touch
	};

/*
4) CLIP_PED_TABLE, size = 8*23 = 184 bits
index = {CLIP_PED_SET}, 8 index
value = {
        CLIP_MULT_STEP, //5 bits, step to increase CLIP_PED1 and 2 if SNR_DELTA > 0
        CLIP_PED1_EN,   //1 bit
        CLIP_PED1,              //8 bits
        CLIP_PED2_EN,   //1 bit
        CLIP_PED2               //8 bits
        }
*/
static const UINT8 CLIP_PED2[8]={
//						-CLIP_PED_SET			
			0x73,		//  8psk 3/5
			0x80,		//	8psk 2/3
			0x95,		//	010
			0x20,			//	011
			0x73,			//  100
			0,			//	101
			0,			//	110
			0			//	111
	
	};
static const UINT8 CLIP_PED2_EN[8]={
//						-CLIP_PED_SET			
			0x1,		//  8psk 3/5
			0x1,		//	8psk 2/3
			0x0,			//	010
			0x1,			//	011
			0,			//  100
			0,			//	101
			0,			//	110
			0			//	111
	
	};
static const UINT8 CLIP_PED1[8]={
//						-CLIP_PED_SET			
			0x37,		//  8psk 3/5
			0x90,		//	8psk 2/3
			0x50,			//	8psk 3/4
			0x30,			//	011
			0x37,			//  100
			0,			//	101
			0,			//	110
			0			//	111
	
	};
static const UINT8 CLIP_PED1_EN[8]={
//						-CLIP_PED_SET			
			0x1,		//  8psk 3/5
			0x1,		//	8psk 2/3
			0x0,			//	8psk 3/4
			0x1,			//	011
			0,			//  100
			0,			//	101
			0,			//	110
			0			//	111
	
	};
static const UINT8 CLIP_MULT_STEP[8]={
//						-CLIP_PED_SET			
			0x0,		//  8psk 3/5
			0x0,		//	8psk 2/3
			0,			//	010
			0x0f,			//	011
			0,			//  100
			0,			//	101
			0,			//	110
			0			//	111
	
	};

/*
5) AVG_PED_TABLE, size = 8*26 = 224 bits
index = {code_rate}, 8 index
value = {
        AVG_SNR_DELTA,  //3 bits SNR_DELTA to apply AVG_PED
        AVG_MULT_STEP,  //5 bits, step to increase AVG_PED1 and 2 if SNR_DELTA > AVG_SNR_DELTA
        AVG_PED1_EN,    //1 bit 
        AVG_PED1,               //8 bits
        AVG_PED2_en,    //1 bit
        AVG_PED2,               //8 bits
        }
*/
static const UINT8 AVG_PED2[8]={
//						-AVG_PED_SET			
		0x32,			//  8psk 3/5
		0x18,			//	8psk 2/3
		0x70,				//	010
		0x05,				//	011
		0x46,				//  100
		0x32,				//	101
		0,				//	110
		0				//	111
	};
static const UINT8 AVG_PED2_en[8]={
//						-AVG_PED_SET			
		0x1,			//  8psk 3/5
		0x1,				//	8psk 2/3
		1,				//	010
		1,				//	011
		1,				//  100
		1,				//	101
		0,				//	110
		0				//	111
	};
static const UINT8 AVG_PED1[8]={
//						-AVG_PED_SET			
		0x96,			//  8psk 3/5
		0x30,			//	8psk 2/3
		0xe0,				//	010
		0x0a,				//	011
		0x96,				//  100
		0x96,				//	101
		0,				//	110
		0				//	111
	};
static const UINT8 AVG_PED1_EN[8]={
//						-AVG_PED_SET			
		0x1,			//  8psk 3/5
		0x1,			//	8psk 2/3
		1,				//	010
		1,				//	011
		1,				//  100
		1,				//	101
		0,				//	110
		0				//	111
	};
static const UINT8 AVG_MULT_STEP[8]={
//						-AVG_PED_SET			
		0x0,			//  8psk 3/5
		0x0,			//	8psk 2/3
		0,				//	010
		0,				//	011
		0,				//  100
		0,				//	101
		0,				//	110
		0				//	111
	};
static const UINT8 AVG_SNR_DELTA[8]={
//						-AVG_PED_SET			
		0x1,			//  8psk 3/5
		0x1,			//	8psk 2/3
		0,				//	
		0,				//	
		0,				//  
		0,				//	
		0,				//	
		0				//	
	};
/*
1) S_CODE_RATE_TABLE size = 6*30 = 180 bits
index = {code_rate}, 6 index
value = { //30 bits
        S_AWGN_NOISE,             //10 bits, EST_NOISE (MSBs) level to apply AWGN coefficients
        S_AWGN_COEF_SET,  //3 bit, select one set from the AWGN_COEF table
        S_PON_IRS_DELTA,  //3 bit signed, subtract from AWGN IRS when Pilot On
        S_PON_PRS_DELTA,  //3 bit signed, subtract from AWGN PRS when Pilot On
        S_LOOP_COEF_SET,  //3 bit, select one set from the CLIP_PED table
        S_CLIP_PED_SET,   //3 bit, select one set from the CLIP_PED table
        S_AVG_PED_SET,    //3 bit, select one set from the AVG_PED table
        S_FORCE_OLD_CR,   //1 bit, only affect pilot off
        S_LLR_SHIFT              //1 bit
        } 
code_rate = PL_MODCOD_TYPE[6:2]-1;

*/

static const UINT16 S_AWGN_NOISE[6]={// dont need to change
	0x0,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
	};

static const UINT8 S_AWGN_COEF_SET[6]={
	0x4,
	0x4,
	0x4,
	0x4,
	0x4,
	0x4
	};

static const UINT8 S_PON_IRS_DELTA[6]={//dont need to change
	0x0,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
	};

static const UINT8 S_PON_PRS_DELTA[6]={//dont need to change
	0x0,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
	};

static const UINT8 S_LOOP_COEF_SET[6]={
	0x4,
	0x4,
	0x4,
	0x4,
	0x4,
	0x4

	};

static const UINT8 S_CLIP_PED_SET[6]={
	0x2,
	0x2,
	0x2,
	0x2,
	0x2,
	0x2
	};

static const UINT8 S_AVG_PED_SET[6]={
	0x6,
	0x6,
	0x6,
	0x6,
	0x6,
	0x6
	};

static const UINT8 S_FORCE_OLD_CR[6]={
	0x1,
	0x1,
	0x1,
	0x1,
	0x1,
	0x1
	};

static const UINT8 S_LLR_SHIFT[6]={
	0x0,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
	};
  //-End: TAB for New ADPT Add by Hongyu //
//----------------end of defines for CR adaptive----------------
/* 3503 register define for DVBS/DVBS2 */
enum NIM3501_REGISTER_ADDRESS
{
	R00_CTRL = 0x00,			// NIM3501 control register 				
	R01_ADC = 0x01,				// ADC Configuration Register
	R02_IERR = 0x02,			// Interrupt Events Register
	R03_IMASK = 0x03,			// Interrupt Mask Register
	R04_STATUS = 0x04,			// Status Register
	R05_TIMEOUT_TRH = 0x05,		// HW Timeout Threshold Register(LSB)
	R07_AGC1_CTRL = 0x07,		// AGC1 reference value register
	R0A_AGC1_LCK_CMD = 0x0a,	// AGC1 lock command register
	R0E_ADPT_CR_CTRL = 0x0e,
	R10_DCC_CFG = 0x10,			// DCC Configure Register
	R11_DCC_OF_I = 0x11,		// DCC Offset I monitor Register
	R12_DCC_OF_Q = 0x12,		// DCC Offset Q monitor Register
	R13_IQ_BAL_CTRL = 0x13,		// IQ Balance Configure Register
	R15_FLT_ROMINDX = 0x15,		// Filter Bank Rom Index Register
	R16_AGC2_REFVAL = 0x16,		// AGC2 Reference Value Register
	R17_AGC2_CFG = 0x17,		// AGC2 configure register
	R18_TR_CTRL = 0x18,			// TR acquisition gain register
	R1B_TR_TIMEOUT_BAND = 0x1b,	// TR Time out band register
	R21_BEQ_CTRL = 0x21,		// BEQ Control REgister
	R22_BEQ_CMA_POW = 0x22,		// BEQ CMA power register
	R24_MATCH_FILTER = 0x24,	// Match Filter Register
	R25_BEQ_MASK = 0x25,		// BEQ Mask Register
	R26_TR_LD_LPF_OPT = 0x26,	// TR LD LPF Output register
	R28_PL_TIMEOUT_BND = 0x28,	// PL Time out Band REgister
	R2A_PL_BND_CTRL = 0x2a,		// PL Time Band Control
	R2E_PL_ANGLE_UPDATE = 0x2e,	// PL Angle Update High/Low limit register
	R30_AGC3_CTRL = 0x30,		// AGC3  Control Register
	R33_CR_CTRL = 0x33,			// CR DVB-S/DVBS-S2  CONTROL register
	R45_CR_LCK_DETECT = 0x45,	// CR lock detecter lpf monitor register
	R47_HBCD_TIMEOUT = 0x47,	// HBCD Time out band register
	R48_VITERBI_CTRL = 0x48,	// Viterbi module control register
	R54_VITERBI_FRAME_SYNC=0x54,
	R57_LDPC_CTRL = 0x57,		// LDPC control register
	R5B_ACQ_WORK_MODE = 0x5b,	// Acquiescent work mode register
	R5C_ACQ_CARRIER = 0x5c,		// Acquiescent carrier control register
	R5F_ACQ_SYM_RATE = 0x5f,	// Acquiescent symbol rate register
	R62_FC_SEARCH = 0x62,		// FC Search Range Register
	R64_RS_SEARCH = 0x64,		// RS Search Range Register
	R66_TR_SEARCH = 0x66,		// TR Search Step register
	R67_VB_CR_RETRY = 0x67,		// VB&CR Maximum Retry Number Register
	R68_WORK_MODE = 0x68,		// Work Mode Report Register
	R69_RPT_CARRIER = 0x69,		// Report carrier register
	R6C_RPT_SYM_RATE = 0x6c,	// report symbol rate register
	R6F_FSM_STATE = 0x6f,		// FSM State Moniter Register
	R70_CAP_REG = 0x70,			// Capture Param register
	R74_PKT_STA_NUM = 0x74,		// Packet Statistic Number Register
	R76_BIT_ERR = 0x76,			// Bit Error Register
	R79_PKT_ERR = 0x79,			// Packet Error Register
	R7B_TEST_MUX = 0x7b,		// Test Mux Select REgister
	R7C_DISEQC_CTRL = 0x7c,		// DISEQC Control Register
	R86_DISEQC_RDATA = 0x86,	// Diseqc data for read
	R8E_DISEQC_TIME = 0x8e,		// Diseqc time register
	R90_DISEQC_CLK_RATIO = 0x90,// Diseqc clock ratio register
	R97_S2_FEC_THR = 0x97,		// S2 FEC Threshold register
	R99_H8PSK_THR = 0x99,		// H8PSK CR Lock Detect threshold register
	R9C_DEMAP_BETA = 0x9c,		// Demap Beta register
	R9D_RPT_DEMAP_BETA = 0x9d, // Report demap beta value / CR Table addr
	RA0_RXADC_REG = 0xa0,		// RXADC ANATST/POWER register
	RA3_CHIP_ID = 0xa3,			// Chip ID REgister
	RA5_VER_ID = 0xa5,			// version ID register
	RA6_VER_SUB_ID = 0xa6,			// version sub ID register
	RA7_I2C_ENHANCE = 0xa7,		// I2C Enhance Register
	RA8_M90_CLK_DCHAN = 0xa8,	// M90 clock delay chain register
	RA9_M180_CLK_DCHAN = 0xa9,	// M180 Clock delay chain register
	RAA_S2_FEC_ITER = 0xaa,		// S2 FEC iteration counter register
	RAB_CHIP_SUB_ID = 0xab,		// S2 FEC iteration counter register	
	RAD_TSOUT_SYMB = 0xad,		// ts  out setting SYMB_PRD_FORM_REG
	RAF_TSOUT_PAD = 0xaf,		// TS out setting and pad driving register
	RB0_PLL_CONFIG = 0xb0,		// PLL configure REgister
	RB1_TSOUT_SMT = 0xb1,		// TS output Setting and Pad driving
	RB3_PIN_SHARE_CTRL = 0xb3,	// Pin Share Control register
	RB5_CR_PRS_TRA = 0xb5,		// CR DVB-S/S2 PRS in Tracking State
	RB6_H8PSK_CETA = 0xb6,		// H8PSK COS/SIN Ceta Value Register
	RB8_LOW_RS_CLIP = 0xb8,		// Low RS Clip Value REgister 	
	RBA_AGC1_REPORT = 0xba,		// AGC1 report register
	RBB_SNR_RPT1 = 0xbb,
	RBC_SNR_RPT2 = 0xbc,
	RBD_CAP_PRM = 0xbd,			// Capture Config/Block register
	RBF_S2_FEC_DBG = 0xbf,		// DVB-S2 FEC Debug REgister
	RC0_BIST_LDPC_REG = 0xc0,	// LDPC Average Iteration counter register
	RC1_DVBS2_FEC_LDPC = 0xc1,	// DVBS2 FEC LDPC Register
	RC8_BIST_TOLERATOR = 0xc8,	// 0xc0	Tolerator MBIST register
	RC9_CR_OUT_IO_RPT = 0xc9,	// Report CR OUT I Q
	// for s3501B
	RCB_I2C_CFG = 0xcb,			// I2C Slave Configure Register
	RCC_STRAP_PIN_CLOCK = 0xcc,	// strap pin and clock enable register
	RCD_I2C_CLK = 0xcd,			// I2C AND CLOCK ENABLE REGISTER
	RCE_TS_FMT_CLK = 0xce,		// TS Format and clock enable register
	RD0_DEMAP_NOISE_RPT = 0xd0,	// demap noise rtp register
	RD3_BER_REG = 0xd3,			// BER register
	RD6_LDPC_REG = 0xd6,		// LDPC register
	RD7_EQ_REG = 0xd7,			// EQ register
	RD8_TS_OUT_SETTING = 0xd8,	// TS output setting register
	RD9_TS_OUT_CFG = 0xd9,		// BYPASS register
	RDA_EQ_DBG = 0xda,			// EQ Debug Register
	RDC_EQ_DBG_TS_CFG = 0xdc,	// EQ debug and ts config register
	RDD_TS_OUT_DVBS = 0xdd,		// TS output dvbs mode setting
	RDF_TS_OUT_DVBS2 = 0xdf,	// TS output dvbs2 mode setting
	RE0_PPLL_CTRL = 0xe0,
	RF0_HW_TSO_CTRL = 0xf0,
	RF1_DSP_CLK_CTRL = 0xf1,
	RF8_MODCOD_RPT = 0xf8,
	RFA_RESET_CTRL = 0xfa,
	RFF_TSO_CLS = 0xff,
	R113_NEW_CR_ADPT_CTRL = 0x113,
	R114_DISEQC_TIME_SET = 0x114,
    R11C_MAP_IN_I=0x11c,
	R124_HEAD_DIFF_NFRAME = 0x124,
    R12d_LDPC_SEL = 0x12d,
	R130_CR_PARA_DIN = 0x130,
	R13b_EST_NOISE = 0x13b,
	R13d_ADPT_CR_PARA_0 = 0x13d,
	R140_ADPT_CR_PARA_1 = 0x140,
	R144_ADPT_CR_PARA_2 = 0x144,
};

struct nim_s3501_TskStatus
{
	UINT32 m_lock_flag;
	ID m_task_id;
	UINT32 m_sym_rate;
	UINT8 m_work_mode;
	UINT8 m_map_type;
	UINT8 m_code_rate;
	UINT8 m_info_data;
};
struct nim_s3501_TParam
{
	int t_last_snr;		
	int t_last_iter;
	int t_aver_snr;
	int t_snr_state;
	int t_snr_thre1;
	int t_snr_thre2;
	int t_snr_thre3;
	INT32 t_phase_noise_detected;
	INT32 t_dynamic_power_en;
	UINT32 phase_noise_detect_finish;
	UINT32 t_reg_setting_switch;
	UINT8 t_i2c_err_flag;
};
struct nim_s3501_LStatus
{
	ID nim_s3501_sema;
	ER ret;
	UINT8 s3501_autoscan_stop_flag;
	UINT8 s3501_chanscan_stop_flag;
	UINT32 old_ber ;
	UINT32 old_per ;
	UINT32 old_ldpc_ite_num;
	UINT8 *ADCdata;// = (unsigned char *)__MM_DMX_FFT_START_BUFFER;//[2048];
	UINT8 *ADCdata_malloc_addr;
	UINT8 *ADCdata_raw_addr;
	INT32 m_Freq[256];
	UINT32 m_Rs[256];
	INT32 FFT_I_1024[1024];
	INT32 FFT_Q_1024[1024];
	UINT8 m_CRNum;
	UINT32 m_CurFreq;
	UINT8 c_RS ;
	UINT32 m_StepFreq;
	pfn_nim_reset_callback m_pfn_reset_s3501;
	UINT8 m_enable_dvbs2_hbcd_mode;
	UINT8 m_dvbs2_hbcd_enable_value;
	UINT8 s3501d_lock_status;
	UINT32 phase_err_check_status;
	UINT32 m_s3501_type;
	UINT32 m_s3501_sub_type;
	UINT32 m_setting_freq;
	UINT32 m_Err_Cnts;
	UINT8 m_hw_timeout_thr;
};
enum NIM_BLSCAN_MODE
{
    NIM_SCAN_FAST = 0,
	NIM_SCAN_SLOW = 1,
};
	
struct nim_s3501_private
{
	INT32 	(*nim_Tuner_Init) (UINT32 *, struct QPSK_TUNER_CONFIG_EXT *);	// Tuner Initialization Function
	INT32 	(*nim_Tuner_Control) (UINT32, UINT32, UINT32);	// Tuner Parameter Configuration Function
	INT32 	(*nim_Tuner_Status) (UINT32, UINT8 *);	
	struct   QPSK_TUNER_CONFIG_DATA Tuner_Config_Data;
	UINT32 tuner_id;
	UINT32 i2c_type_id;
	UINT32 polar_gpio_num;
	UINT32 sys_crystal;
	UINT32 sys_clock;
	UINT16 pre_freq ;
	UINT16 pre_sym ;
	INT8 autoscan_stop_flag ;
	struct nim_device_stats stats;
	UINT8 chip_id;
	struct EXT_DM_CONFIG ext_dm_config;
	struct nim_s3501_LStatus ul_status;
	INT32 ext_lnb_id;
	INT32 	(*ext_lnb_control) (UINT32, UINT32, UINT32);
	struct nim_s3501_TskStatus tsk_status;
	struct nim_s3501_TParam t_Param;
	UINT32 cur_freq;
	UINT32 cur_sym;	
	UINT32 flag_id;
	enum NIM_BLSCAN_MODE blscan_mode;
	OSAL_ID m3501_mutex;
};



//INT32 nim_s3503_attach(struct nim_device *dev, struct QPSK_TUNER_CONFIG_API *ptrQPSK_Tuner);
INT32 nim_s3503_attach(struct QPSK_TUNER_CONFIG_API *ptrQPSK_Tuner);
INT32 nim_s3503_ioctl_ext(struct nim_device *dev, INT32 cmd, void *param_list);
INT32 nim_s3503_WidebandScan_open(struct nim_device *dev,UINT32 start_freq, UINT32 end_freq,UINT32 step_freq);
INT32 nim_s3503_WidebandScan_close();
INT32 nim_s3503_WidebandScan(struct nim_device *dev,UINT32 start_freq, UINT32 end_freq);

//Nim Autosearch,R2FFT 
extern INT32 nim_s3501_autosearch(INT32 *success, INT32 *delta_fc_est, INT32 *SymbolRate_est, INT32 *m_IF_freq, INT32 *m_ch_number);
extern void nim_s3501_smoothfilter(void);
extern  void nim_s3501_MedianFilter(INT32 FLength, INT32 *Fdata, INT32 Scan_mode);
extern INT32 nim_s3501_SearchTP(INT32 chlspec_Num, 
							INT32 *channel_spectrum,
							UINT32 sfreq,
							UINT32 ADC_sample_freq,
							INT32 loop);
extern INT32 nim_s3501_FFT_WidebandScan(struct nim_device *dev,UINT32 Tuner_IF,UINT32 ADC_sample_freq);
extern void R2FFT(INT32 *FFT_I_1024, INT32 *FFT_Q_1024);
//demux signal pass
extern INT32 nim_s3501_autoscan_signal_input(struct nim_device *dev, UINT8 s_Case);

#endif	// __LLD_NIM_S3501_H__ */


